1. Field of the Invention
The present invention relates to bus hold circuits. In particular, the present invention relates to bus hold circuits established using Complementary Metal Oxide Semiconductor (CMOS) transistor-based technology. More particularly, the present invention relates to CMOS-based bus hold circuits designed to protect against unintended switching or bus coupling caused by overvoltage conditions.
2. Description of the Prior Art
Circuit buses are used to transfer electrical signals of desired amplitude and strength between and among assorted computing and peripheral devices. Circuit buses may connect two or more such devices together either when the devices are proximate to one another or remote from one another. The devices associated with bus interconnections include macro devices such as computers, printers, communications devices, and the like. They also include internal components such as microprocessors, memory cells, etc. Buses are generally simply lines of conductive material that enable rapid signal transfer. However, it is necessary to regulate the signal flow through a bus so that signal exchange and processing may be properly coordinated through the coupled devices. In order to do that, all devices designed to communicate with other coupled devices include bus-interface input and output circuits. These bus-interface circuits are designed to regulate out-going signal transmission to the bus for delivery to another device or devices, and in-coming signal reception from such other devices via the bus.
With a plurality of devices linked to a bus, it is necessary to ensure that only one of those devices has access to the bus at a time in order to avoid the transmission of conflicting signals. All other devices linked to the bus are required to present a high-impedance condition to the bus so that no unintended signal transfer may occur. Thus, to that end, with a system active, a bus-interface circuit must exist in any one of three defined states at any one time. The first state is a first bus-drive condition designed to transfer the equivalent of a logic low signal, the second is a second bus-drive condition designed to transfer the equivalent of a logic high signal, and the third the equivalent of a high-impedance or standby state. The bus-interface circuits designed to regulate signal transfer with the bus are generally known as three-state or tristate buffers.
Bus-interface circuits take many forms. In one fairly standard example, the bus-interface circuit is simply an inverter and latch combination designed to receive a signal of sufficient potential for inversion and transmission as shown in the example of FIG. 1. Specifically, the prior-art teaches to couple a latching inverter IV2 in anti-parallel with the input inverter IV1 as shown in FIG. 1 for prior bus-hold circuit 10. High-potential power rail Vcc and low-potential power rail GND power both inverters IV1 and IV2. The latching inverter IV2 is designed to latch the input inverter IV1 in its last driven state when it is in a three-state or "Z" impedance condition thus creating a bus-hold circuit. The incoming signal at IN may be from related circuitry associated with the circuit 10 of a particular device which signal is to be supplied to the bus via node OUT. Alternatively, the signal at IN may be from the bus with the output signal at OUT being delivered to that coupled device circuitry.
Under certain conditions, a signal applied to the input of the bus-interface circuit 10 may be at a potential varying from the potential range under which the inverter is designed to operate. This is an increasing issue as devices of mixed potential ranges are coupled together through a common bus. In certain circumstances, and in particular when the latching inverter IV2 is a CMOS inverter, excess potential at the output node of that inverter can cause a turning on of both CMOS transistors such that significant leakage current will pass between rails Vcc and GND.
It is well known that in digital systems the signals moving between devices are categorized as either logic level high (or "1" or "ON") and logic level low (or "0" or "OFF"). The particular signal potential that defines whether a logic high or a logic low is being transmitted is dependent upon the semiconductor components that form the circuitry associated with that transmission. The most common circuit configurations used to produce digital signals include, among others, CMOS and Transistor-Transistor Logic (TTL). These logic configurations operate differently as a function of the "swing" between what constitutes a logic high signal and what constitutes a logic low signal.
For CMOS logic, which is based primarily on the use of relatively slower, less-power-consuming MOS transistors, a logic low signal is generally developed in the range moving downward from about 0.6 volts (V) above a low-potential power rail GND, which may be at 0.0V. A logic high signal is generally developed in the range of Vcc to Vcc-0.6V, where Vcc may vary between 4.5V and 5.5V for a nominal 5-volt supply, or between 3.0V and 3.6V for a nominal 3.3-volt supply. For a 3.3-volt supply then, the differential swing between low and high must be at least 2.4 volts in order to ensure that a desired shift between a logic low and a logic high will occur. Relatedly, for a system that is 3.3-volt based, a signal received from a device at full-rail 5-volt nominal potential may overwhelm that system. Thus, in mating 5-volt and 3-volt systems, as well as in mating other systems of unequal power supplies, logic potentials outside of the intended range must be accounted for. That is particularly the case for a CMOS-based inverter that is a three-state bus-hold circuit. If the particular inverter is supplied by a 3.3-V high-potential power rail and the input signal to that inverter exceeds the full-rail potential for example, an overvoltage condition occurs and the inverter may be unintentionally activated so as to conduct a signal, or will otherwise conduct current between the high and low power rails as noted in regard to inverter IV2 of FIG. 1.
The increasing likelihood of overvoltage conditions at the input to the input inverter due to the increase in the coupling of mixed-potential devices requires a solution. Since overvoltage conditions may occur in the bus-hold circuit 10 of FIG. 1, clamping components such as Schottky diode SD have been employed between the output of feedback latching inverter IV2 and input inverter IV1 in second bus-hold circuit 11 shown in FIG. 2. Specifically, when an overvoltage condition occurs at the input IN, the Schottky diode blocks that excess potential from causing a leakage current condition through inverter IV2. When circuit 11 is powered by a relatively lower supply potential, such as 3.3V for example, it can easily be subjected to an overvoltage condition when coupled at IN to a 5-V based device. Since many Schottky diodes have threshold turn-on potentials of about 0.4 V, the drop across that diode pulls down an otherwise logic high potential at the input to IV1 below the nominal 3.3 V potential of Vcc.
Ordinarily, that sort of drop will not significantly affect the operation of the input inverter IV1 in that a full-rail input is only reduced to about 2.9 V-well within the requirements of a 3.3-V based MOS transistor. However, Schottky diodes are fabricated using bipolar transistor fabrication processes. Those processes are more expensive and time-consuming than those associated with CMOS structures, particularly when only a single device is needed as part of a circuit. Therefore, it is preferable to have a CMOS-based structure that includes a means to address the overvoltage condition. Such a device could be a diode-wired MOS transistor. However, the drop across such a device approaches 1.0 V and may therefore cause the potential at the input of IV1 to be less than what is needed for proper operation to trigger either pull up or pull down without simultaneous conduction therethrough. What is needed is a CMOS-only based bus-hold circuit suitable for use in mixed-supply-potential applications.
U.S. Pat. No. 5,828,233 issued to Nguyen et al. describes a CMOS-based bus-hold circuit for use in mixed-signal conditions. Nguyen apparently employs a passive system of MOS transistors that require overvoltages at the input of greater than threshold potential Vt to trigger blocking of the condition. For MOS transistors that Vt is about 0.7 V. Similarly, the input potential must drop below the potential of Vcc by the same Vt potential before the bus-hold circuit begins to respond to the input signal. Clearly, a potential range of about 1.4 V during which bus-hold circuit operation may be ambiguous is unacceptable.
Therefore, what is needed is a CMOS-only bus-hold circuit having an active system for resolving overvoltage conditions, particularly in regard to the coupling of systems of differing supply potentials. What is also needed is such a circuit that is activated to address overvoltage conditions relatively close to the supply potential for the bus-hold circuit. Further, what is needed is such an active circuit that responds to input signal changes with minimal delay subsequent to resolving an overvoltage condition. Such a circuit must further remain effective in all three states of operation during standard potential conditions.